Define a unit test1. Define the following elements in this unit.
Event p_clk is the rising edge of the HDL signal ~/top/clock.
Event ready is the rising edge of the HDL signal ~/top/ready.
Define TCM ready_cycle() with @p_clk as the sampling event.
First TCM action is to wait for 5 cycles of @p_clk.
Second TCM action is to wait for 6 cycles of @ready @p_clk.
Third TCM action is to wait for 10 cycles of @p_clk.
Fourth TCM action is to print "Ready cycle complete" using the out() action.
End the TCM.
Extend the run() method of test1.
Inside the run() method, start ready_cycle().
Extend the struct sys.
Instantiate the unit test1 under sys.
Extend the unit test1. Define the following elements in this unit.
Extend TCM ready_cycle().
Add a print "Ready cycle start" to the beginning of the TCM using the out() action.
Add a sync @ready after this print.
Create a struct data. Define the following fields in this struct.
address (8 bits).
Constraint on address to be in range 10..20.
data (16 bits).
Constraint on data to be in range 120..200.
Extend the unit test1. Define the following elements in unit test1.
Instantiate the struct data. The instance name is data1. Mark it as a do-not-generate field.
Extend TCM ready_cycle().
Declare a local variable count.
Generate value for count using the gen action.
Write a for loop from 0 to count-1.
In the loop, generate a value for data1 using the gen action.
Add additional constraints for generation of data1, address to be in range 15..17 and data to be in range 150..180.
Print the values of the fields of data1 using the print action.
End the for loop.
End the TCM extension.
End the extension for unit test1.
Explain how to call Verilog tasks and functions from e code.
Explain how to call VHDL procedures and functions from e code.