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8.5 Using HDL Tasks and Functions

In TCMs, it is possible to call HDL tasks and functions directly from e code. This is useful when there are existing bus functional models (BFMs) in HDL that are already proven to work. Figure 8-7 shows such a scenario.

Figure 8-7. Use of HDL Task and Function Calls in e

graphics/08fig07.gif

8.5.1 Verilog Task

A Verilog task definition is a statement or a unit member. The syntax for a Verilog user-defined task or system task in e so that it can be called from a TCM is as follows:

verilog task 'HDL-pathname' (verilog-task-parameter[, ...]);

Example 8-8 shows the usage of a Verilog task call from e code.

Example 8-8 Verilog Task
Example shows the usage of a Verilog task call from
e code.
<'
struct mem_w {
    addr: int;
    data: int(bits: 64);
};

unit receiver {
    verilog task 'top.write_mem' //Actual task in Verilog top module
      (addr:32:in,data:64:out,status:32:out);
                                  //Arguments of the above Verilog
                                  //task. 32, 64 etc are arg widths
    event mem_read_enable; //Event definition.

    get_mem(mw: mem_w) @mem_read_enable is { //Define TCM
        var error_status: int; //Local variable

        //Call the write_mem task defined in Verilog 'top' module
        'top.write_mem'(mw.addr, mw.data, error_status);
        check that error_status == 0; //
    };
};
'>

8.5.2 Verilog Function

A Verilog function definition is a statement or a unit member. The syntax for a Verilog user-defined function or system task in e so that it can be called from a TCM is as follows:

verilog function 'HDL-pathname' (verilog-function-parameter[, ... ]): result-size-exp ;

Example 8-9 shows the usage of a Verilog function call from e code.

Example 8-9 Verilog Function
Example shows the usage of a Verilog function call from
e code.
<'
//Verilog function statement, defined outside of unit
//Two arguments addr (32 bits), data (64 bits).
//Return value of function is 32 bits wide.
verilog function 'top.write_mem'(addr:32,data:64):32;

unit memory_driver {
    event mem_enable is rise ('top.enable') @sim;
    write() @mem_enable is {
        var error_status: int;
        error_status = 'top.write_mem'(31,45); //Call function
    };
};
'>

8.5.3 VHDL Procedure

A VHDL procedure definition is a statement or a unit member. The syntax for a VHDL procedure or system task in e so that it can be called from a TCM is as follows:

vhdl procedure 'identifier' using option, ... ;

Example 8-10 shows the usage of a VHDL procedure call from e code.

Example 8-10 VHDL Procedure
Example shows the usage of a VHDL procedure call from
e code.
<'
unit transactor {
    vhdl procedure 'send_packet' using library="work",
        package="pkg";

    test() @sys.clk is {
        'work.pkg.send_packet'(); //Call VHDL procedure
    };
};

extend sys {
    event clk is rise ('top.clk') @sim;

    transactor1: transactor is instance;
    transactor2: transactor is instance;

    run() is also {
        start transactor1.test();
        start transactor2.test();
    };
};
'>

8.5.4 VHDL Function

A VHDL function definition is a statement or a unit member. The syntax for a VHDL procedure or system task in e so that it can be called from a TCM is as follows:

vhdl function 'identifier' using option, ...;

Example 8-11 shows the usage of a VHDL function call from e code.

Example 8-11 VHDL Function
Example shows the usage of a VHDL function call from
e code.
<'
//VHDL function statement
vhdl function 'increment' using
    interface="(a: integer) return integer",
    library="work", package="pkg", alias="integer_inc_1";

//VHDL function statement
vhdl function 'increment' using
    interface="(a: integer; n: integer) return integer",
    library="work", package="pkg",
    alias="integer_inc_n";

extend sys {
    event clk is rise ('top.clk') @sim;

    test(a:int)@clk is { //Define a TCM
       //Make calls to VHDL functions
       check that 'integer_inc_1'(a) == 'integer_inc_n'(a,1);
    };
};
'>
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