Define a struct test1. Instantiate the struct test1 under sys. Define the following events in this struct. (Hint: Default sampling event is @sim. Although minimal numbers of @sim events should be used in e code, this exercise uses them for simplicity.)
Event a_event.
Event p_clk is the rising edge of the HDL signal ~/top/clock.
Event n_clk is the falling edge of the HDL signal ~/top/clock.
Event c_clk is either edge of the HDL signal ~/top/clock.
Event rst is emitted when the HDL signal ~/top/reset is 1 at sampling event p_clk (this is a synchronous reset).
Extend the struct test1. Add the following events to the struct test1.
Event p_start is the rising edge of the HDL signal ~/top/packet_valid.
Event p_end is the falling edge of the HDL signal ~/top/packet_valid.
Event p_ack is the rising edge of the HDL signal ~/top/packet_ack.
Event p_pulse is the rising edge of the HDL signal ~/top/packet_pulse.
Extend the struct test1. Redefine the following event in struct test1 using the is only syntax.
Event a_event is emitted if both p_start and p_pulse are emitted in the same sampling period. The sampling event is @p_clk.
Extend the struct test1. Define the following events in struct test1.
Event b_event is emitted if either p_start or p_pulse is emitted in the same sampling period. The sampling event is @p_clk.
Event c_event is emitted if fail {p_start; p_ack} succeeds in a sampling period. The sampling event is @p_clk.
Event d_event is emitted if not {p_start; p_ack} succeeds in a sampling period. The sampling event is @p_clk.
Event e_event is emitted if p_start is immediately followed by 25 to 50 clock cycles and then immediately followed by p_ack. The sampling event is @p_clk.
Event f_event is emitted if p_start is followed eventually by p_ack. The sampling event is @p_clk.
Event g_event is emitted if p_start is immediately followed by three emissions of p_pulse, followed by five clock cycles and then immediately followed by p_ack. The sampling event is @p_clk.