This section describes the complete DUT specification of a simple router design. This is not as big as a real router but mimics the basic functionality of a real router in a simple manner.
Figure 12-1 shows the input/output specification of the DUT.
The router accepts data packets on a single 8-bit input port called data and routes the packets to one of the three output channels, channel0, channel1, and channel2. In a typical router, packets are accepted from a packet driver ASIC or line card. Similarly, output packets are routed to a packet receiver ASIC or line card. Other I/O signals are described later in this section.
A packet is a sequence of bytes with the first byte containing a header, the next variable set of bytes containing data, and the last byte containing parity. The packet format has the following characteristics.
The header consists of a 2-bit address field and a 6-bit length field.
The address field is used to determine to which output channel the packet should be routed, with address "3" being illegal.
The length field specifies the number of data bytes (payload). A packet can have a minimum data size of 1 byte and a maximum data size of 63 bytes.
The parity should be a byte of even, bitwise parity, calculated over the header and data bytes of the packet.
Figure 12-2 shows the format of a data packet. The data packet is modeled as a struct.
Figure 12-3 shows the input protocol for the DUT.
The characteristics of the DUT input protocol are as follows:
All input signals are active high and are synchronized to the falling edge of the clock. Therefore, any signal that is an input to the DUT is driven at the falling edge of clock. This is because the DUT router is sensitive to the rising edge of clock. Therefore, driving input signals on the falling edge ensures adequate setup and hold time. Since this is a functional simulation rather than a timing simulation, this specification will suffice.
The packet_valid signal has to be asserted on the same clock as when the first byte of a packet (the header byte), is driven onto the data bus.
Since the header byte contains the address, this tells the router to which output channel the packet should be routed (channel0, channel1, or channel2).
Each subsequent byte of data should be driven on the data bus with each new falling clock.
After the last payload byte has been driven, on the next falling clock, the packet_valid signal must be deasserted, and the packet parity byte should be driven. This signals packet completion.
The input data bus value cannot change while the suspend_data_in signal is active (indicating a FIFO overflow). The packet driver should not send any more bytes and should hold the value on the data bus. The width of suspend_data_in signal assertion should not exceed 100 cycles.
The err signal asserts when a packet with bad parity is detected in the router, within 1 to 10 cycles of packet completion.
Figure 12-4 shows the output protocol for the DUT.
The characteristics of the DUT output protocol are as follows:
All output signals are active high and are synchronized to the falling edge of the clock. Thus, the packet receiver will drive sample data at the falling edge of clock. This is correct because the router will drive and sample data at the rising edge of clock.
Each output port channelX (channel0, channel1 or channel2) is internally buffered by a FIFO of depth 16 and a width of 1 byte.
The router asserts the vld_chan_X (vld_chan_0, vld_chan_1 or vld_chan2) signal when valid data appears on the channelX (channel0, channel1 or channel2) output bus. This is a signal to the packet receiver that valid data is available on a particular router.
The packet receiver will then wait until it has enough space to hold the bytes of the packet and then respond with the assertion of the read_enb_X (read_enb_0, read_enb_1 or read_enb_2) signal that is an input to the router.
The read_enb_X (read_enb_0, read_enb_1 or read_enb_2) input signal is asserted on the falling clock edge in which data are read from the channelX (channel0, channel1 or channel2) bus.
As long the read_enb_X (read_enb_0, read_enb_1 or read_enb_2) signal remains active, the channelX (channel0, channel1 or channel2) bus drives a valid packet byte on each rising clock edge.
The packet receiver cannot request the router to suspend data transmission in the middle of a packet. Therefore, the packet receiver must assert the read_enb_X (read_enb_0, read_enb_1 or read_enb_2) signal only after it ensures that there is adequate space to hold the entire packet.
The read_enb_X (read_enb_0, read_enb_1 or read_enb_2) must be asserted within 30 clock cycles of the vld_chan_X (vld_chan_0, vld_chan_1 or vld_chan2) being asserted. Otherwise, there is too much congestion in the packet receiver.
The DUT channelX (channel0, channel1 or channel2) bus must not be tri-stated (high-Z) when the DUT signal vld_chan_X (vld_chan_0, vld_chan_1 or vld_chan2) is asserted (high) and the input signal read_enb_X (read_enb_0, read_enb_1 or read_enb_2) is also asserted high.
Figure 12-5 shows the state machine transitions for the DUT. All state transitions in the DUT occur at the rising edge of clock.
The legal transitions of the DUT state machine shown in Figure 12-5 above are listed in Figure 12-6. All transitions that are not listed below are illegal transitions. It is important to monitor and report an error message when such transitions happen.