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Preface

During my earliest experience with e, I was looking for a book that could give me a "jump start" on using e. I wanted to learn basic digital verification paradigms and the necessary e constructs that would help me verify small digital designs. After I had gained some experience with building basic e verification environments, I wanted to learn to use e to verify large designs. At that time I was searching for a book that broadly discussed advanced e-based design verification concepts and real design verification methodologies. Finally, when I had gained enough experience with design verification of many multi-million gate chips using e, I felt the need for an e book that would act as a handy reference. I realized that my needs were different at different stages of my design verification maturity. A desire to fill these needs has led to the publication of this book.

Rapid changes have occurred during the past few years. High Level Verification Languages (HVLs) such as e have become a necessity for verification environments. I have seen state-of-the-art verification methodologies and tools evolve to a high level of maturity. I have also applied these verification methodologies to a wide variety of multi-million gate ASICs that I have successfully completed during this period. I hope to use these experiences to make this edition a richer learning experience for the reader.

This book emphasizes breadth rather than depth. The book imparts to the reader a working knowledge of a broad variety of e-based topics, thus giving the reader a global understanding of e-based design verification. The book leaves the in-depth coverage of each topic to the reference manuals and usage guides for e.

This book should be classified not only as an e book but, more generally, as a design verification book. It important to realize that e is only a tool used in design verification. It is the means to an end—the digital IC chip. Therefore, this book stresses the practical verification perspective more than the mere language aspects of e. With HVL-based design verification having become a necessity, no verification engineer can afford to ignore popular HVLs such as e.

Currently, Specman Elite by Verisity Design, Inc., is the only tool that supports e. However, the powerful constructs that e provides for design verification make it an excellent HVL. Because of its popularity, it is likely that e will be standardized in the future and multiple vendors will create tools to support e. Therefore, in this book, although Specman Elite is used as a reference tool, the treatment of e is done in a tool-independent manner. e concepts introduced in this book will be generally applicable in the future regardless of the tool that is used.

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