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12.1 Device Under Test (DUT) Specification

This section describes the complete DUT specification of a simple router design. This is not as big as a real router but mimics the basic functionality of a real router in a simple manner.

12.1.1 Input/Output Specification

Figure 12-1 shows the input/output specification of the DUT.

Figure 12-1. Input/Output Specification of Router

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The router accepts data packets on a single 8-bit input port called data and routes the packets to one of the three output channels, channel0, channel1, and channel2. In a typical router, packets are accepted from a packet driver ASIC or line card. Similarly, output packets are routed to a packet receiver ASIC or line card. Other I/O signals are described later in this section.

12.1.2 Data Packet Description

A packet is a sequence of bytes with the first byte containing a header, the next variable set of bytes containing data, and the last byte containing parity. The packet format has the following characteristics.

Figure 12-2 shows the format of a data packet. The data packet is modeled as a struct.

Figure 12-2. Data Packet Format

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12.1.3 DUT Input Protocol

Figure 12-3 shows the input protocol for the DUT.

Figure 12-3. DUT Input Protocol

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The characteristics of the DUT input protocol are as follows:

12.1.4 DUT Output Protocol

Figure 12-4 shows the output protocol for the DUT.

Figure 12-4. DUT Output Protocol

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The characteristics of the DUT output protocol are as follows:

12.1.5 DUT State Machine

Figure 12-5 shows the state machine transitions for the DUT. All state transitions in the DUT occur at the rising edge of clock.

Figure 12-5. DUT State Machine

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The legal transitions of the DUT state machine shown in Figure 12-5 above are listed in Figure 12-6. All transitions that are not listed below are illegal transitions. It is important to monitor and report an error message when such transitions happen.

Figure 12-6. DUT State Machine Transitions

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