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List of Figures

Figure 1-1 Evolution of Verification

Figure 1-2 HDL Task-Based Strategy

Figure 1-3 Activities in a Verification Environment

Figure 1-4 Constraint Based Generation

Figure 1-5 Driving the Stimulus on to the DUT

Figure 1-6 Data Checking

Figure 2-1 Interaction between Specman Elite and the Simulator

Figure 2-2 e and Verilog Hierarchies

Figure 2-3 Components of a Verification Environment

Figure 2-4 e Verification Environment Hierarchy

Figure 2-5 e Verification Environment Partitioning

Figure 2-6 XOR DUT Description

Figure 2-7 Verilog Hierarchy for XOR Example

Figure 2-8 Interface between Specman Elite and the Simulator for XOR DUT Verification

Figure 2-9 Verification Environment Hierarchy

Figure 2-10 Interaction between Specman Elite and the Simulator for XOR DUT Verification

Figure 3-1 Verification and Design Hierarchies

Figure 3-2 Syntax Hierarchy

Figure 4-1 Extending the Packet Struct

Figure 4-2 Comparison between Structs and Units

Figure 4-3 e Hierarchy of the fast_router

Figure 4-4 DUT Router Hierarchy

Figure 5-1 Generation Hierarchy

Figure 5-2 Applying Constrained Objects on a Design

Figure 5-3 Generic Constraint Solver

Figure 5-4 Generation Decision Chart

Figure 5-5 Order of Generation

Figure 7-1 Sampling Event for a Temporal Expression

Figure 7-2 Example Evaluations of a Temporal Sequence

Figure 7-3 Comparison of Temporal not and fail Operators

Figure 7-4 And Operator

Figure 7-5 Example of Temporal or Operator Behavior

Figure 8-1 Calling TCMs

Figure 8-2 Starting TCMs

Figure 8-3 Usage of Wait and Sync Actions

Figure 8-4 Wait and Sync Actions (Scenario 1)

Figure 8-5 Wait and Sync Actions (Scenario 2)

Figure 8-6 Implicit Sync at the Beginning of Every TCM

Figure 8-7 Use of HDL Task and Function Calls in e

Figure 9-1 Order of Packing

Figure 9-2 Order of Unpacking

Figure 9-3 Comparing Input and Output Structs

Figure 10-1 Coverage Group Items

Figure 11-1 Components of a Verification Environment

Figure 11-2 Driver Object Design

Figure 11-3 Receiver Object Design

Figure 11-4 Data Checker Object Design

Figure 11-5 Scoreboarding Methodology

Figure 11-6 Environment Object Hierarchy

Figure 11-7 Execution Test Phases

Figure 11-8 Two Ways to Launch a TCM from Main TCM

Figure 11-9 Test Phase Methods

Figure 11-10 Specman Elite and HDL Simulator as Independent Processes

Figure 11-11 Synchronization between Specman Elite and HDL Simulator

Figure 12-1 Input/Output Specification of Router

Figure 12-2 Data Packet Format

Figure 12-3 DUT Input Protocol

Figure 12-4 DUT Output Protocol

Figure 12-5 DUT State Machine

Figure 12-6 DUT State Machine Transitions

Figure 12-7 Components of the Router Verification Environment

Figure 13-1 Implementation of Environment Object Hierarchy

Figure 14-1 Traditional Verification Methodology

Figure 14-2 Coverage Improves Stimulus

Figure 14-3 Coverage Improves Checking

Figure 14-4 Coverage Verifies the DUT

Figure 14-5 Coverage Measures Progress

Figure 14-6 Coverage Enables Regression Optimization

Figure 14-7 Code Coverage

Figure 14-8 Functional Coverage

Figure 14-9 Functional vs. Code Coverage

Figure 14-10 Coverage Process

Figure 14-11 Coverage Plan

Figure 14-12 Coverage Driven Verification Environment

Figure 14-13 Coverage Driven Verification Methodology

Figure 15-1 Example DUT

Figure 15-2 XSerial eVC—Dual-Agent Implementation

Figure 15-3 XSerial eVC—Single-Agent Implementation

Figure 15-4 Agent Internals

Figure 15-5 XSoC eVC

Figure 16-1 Integrating e Files and C Files

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