•
Table of Contents
•
Index
Design Verification with
e
By
Samir Palnitkar
Publisher
: Prentice Hall PTR
Pub Date
: September 25, 2003
ISBN
: 0-13-141309-0
Pages
: 416
Copyright
Prentice Hall Modern Semiconductor Design Series
Foreword
Preface
Who Should Use This Book
How This Book is Organized
Conventions Used in This Book
Acknowledgements
List of Figures
List of Tables
List of Examples
Part 1. Introduction
Chapter 1. Overview of Functional Verification
Section 1.1. The Evolution of Verification
Section 1.2. Verification Automation System with
e
Section 1.3. Benefits of
e
Section 1.4. Summary
Chapter 2. Modeling a Verification Environment in
e
Section 2.1. Interaction between Specman Elite and the Simulator
Section 2.2. Structs and Instances
Section 2.3. Components of a Verification Environment
Section 2.4. Verification Example
Section 2.5. Summary
Section 2.6. Exercises
Part 2.
e
Basics
Chapter 3. Basic
e
Concepts
Section 3.1. Conventions
Section 3.2. Data Types
Section 3.3. Simulator Variables
Section 3.4. Syntax Hierarchy
Section 3.5. Summary
Section 3.6. Exercises
Chapter 4. Creating Hierarchy with Structs and Units
Section 4.1. Defining Structs
Section 4.2. Extending Structs
Section 4.3. Defining Fields
Section 4.4. Defining List Fields
Section 4.5. Creating Struct Subtypes with when
Section 4.6. Units
Section 4.7. Summary
Section 4.8. Exercises
Chapter 5. Constraining Generation
Section 5.1. Basic Concepts of Generation
Section 5.2. Basic Constraints
Section 5.3. Implication Constraints
Section 5.4. Soft Constraints
Section 5.5. Weighted Constraints
Section 5.6. Order of Generation
Section 5.7. Constraint Resolution
Section 5.8. Do-Not-Generate Fields
Section 5.9. Summary
Section 5.10. Exercises
Chapter 6. Procedural Flow Control
Section 6.1. Defining Methods
Section 6.2. Conditional Actions
Section 6.3. Iterative Actions
Section 6.4. Useful Output Routines
Section 6.5. Summary
Section 6.6. Exercises
Chapter 7. Events and Temporal Expressions
Section 7.1. Defining Events
Section 7.2. Event Emission
Section 7.3. Event Redefinition
Section 7.4. Sampling Events
Section 7.5. Temporal Operators
Section 7.6. Temporal Expressions
Section 7.7. Predefined Events
Section 7.8. Summary
Section 7.9. Exercises
Chapter 8. Time Consuming Methods
Section 8.1. Defining TCMs
Section 8.2. Invoking TCMs
Section 8.3. Wait and Sync Actions
Section 8.4. Gen Action
Section 8.5. Using HDL Tasks and Functions
Section 8.6. Summary
Section 8.7. Exercises
Chapter 9. Checking
Section 9.1. Packing and Unpacking
Section 9.2. Data Checking
Section 9.3. Temporal Checking
Section 9.4. Summary
Section 9.5. Exercises
Chapter 10. Coverage
Section 10.1. Functional Coverage
Section 10.2. Coverage Groups
Section 10.3. Basic Coverage Item
Section 10.4. Transition Coverage Items
Section 10.5. Cross Coverage Items
Section 10.6. Latency Coverage
Section 10.7. Turning On Coverage
Section 10.8. Viewing Coverage Results
Section 10.9. Summary
Section 10.10. Exercises
Chapter 11. Running the Simulation
Section 11.1. Verification Components
Section 11.2. Execution Flow
Section 11.3. Synchronization between HDL Simulator and Specman Elite
Section 11.4. Summary
Section 11.5. Exercises
Part 3. Creating a Complete Verification System with
e
Chapter 12. Verification Setup and Specification
Section 12.1. Device Under Test (DUT) Specification
Section 12.2. DUT HDL Source Code
Section 12.3. Verification Plan
Section 12.4. Test Plan
Section 12.5. Summary
Chapter 13. Creating and Running the Verification Environment
Section 13.1. Defining the Packet Data Item
Section 13.2. Driver Object
Section 13.3. Receiver Object
Section 13.4. Data Checker Object
Section 13.5. Monitor Object
Section 13.6. Coverage Object
Section 13.7. Environment Object
Section 13.8. Test Scenarios
Section 13.9. Summary
Part 4. Advanced Verification Techniques with
e
Chapter 14. Coverage-Driven Functional Verification
Section 14.1. Traditional Verification Methodology
Section 14.2. Why Coverage?
Section 14.3. Coverage Approaches
Section 14.4. Functional Coverage Setup
Section 14.5. Coverage Driven Functional Verification Methodology
Section 14.6. Summary
Chapter 15. Reusable Verification Components (
e
VCs)
Section 15.1. About
e
VCs
Section 15.2.
e
VC Architecture
Section 15.3.
e
VC Example
Section 15.4. Summary
Chapter 16. Interfacing with C
Section 16.1. C Interface Features
Section 16.2. Integrating C Files
Section 16.3. Accessing the
e
Environment from C
Section 16.4. Calling C Routines from
e
Section 16.5. Calling
e
Methods from C
Section 16.6. C Export
Section 16.7. Guidelines for Using the C Interface
Section 16.8. Linking with C++ Code
Section 16.9. Summary
Part 5. Appendices
Appendix A. Quick Reference Guide
Section A.1. Predefined Types
Type Conversion
Section A.2. Statements
Section A.3. Structs and Unit Members
Section A.4. Actions
Section A.5. Operators
Section A.6. Coverage Groups and Items
Section A.7. Lists
Section A.8. Temporal Language
Section A.9. Packing and Unpacking Pseudo-Methods
Section A.10. Simulator Interface Statements and Unit Members
Section A.11. Preprocessor Directives
Appendix B.
e
Tidbits
Section B.1. History of
e
Section B.2.
e
Resources
Section B.3. Verification Resources
Bibliography
Manuals and References
Books
About the Author
Index