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Conventions Used in This Book

The table below describes the type changes and symbols used in this book.

Visual Cue

Represents

courier

The Courier font indicates e or HDL code. For example, the following line indicates e code:

    keep opcode in [ADD, ADDI];

courier bold

In examples that show commands and their results, Courier bold indicates the commands. For example, the following line shows the usage of the Specman Elite command, load:

    Specman> load test1

bold

The bold font indicates Specman Elite keywords in descriptive text. For example, the following sentence contains two keywords:

Use the verilog trace statement to identify Specman Elite events you want to view in a waveform viewer.

italic

The italic font represents user-defined variables that you must provide. For example, the following line instructs you to type the "write cover" as it appears, and then the actual name of a file:

write cover filename

[ ] square brackets

Square brackets indicate optional parameters. For example, in the following construct the keywords "list of" are optional:

var name: [list of] type

[ ] bold brackets

Bold square brackets are required. For example, in the following construct you must type the bold square brackets as they appear:

extend enum-type-name: [name,…]

construct, …

An item followed by a separator (usually a comma or a semicolon) and an ellipsis is an abbreviation for a list of elements of the specified type. For example, the following line means you can type a list of zero or more names separated by commas.

extend enum-type-name: [name,…]

|

The | character indicates alternative syntax or parameters. For example, the following line indicates that either the bits or bytes keyword should be used:

type scalar-type (bits | bytes: num)

%

Denotes the UNIX prompt.

C1>, C2>, …

Denotes the Verilog simulator prompt.

>

Denotes the VHDL simulator prompt.

Specman>

Denotes the Specman Elite prompt.

A few other conventions need to be clarified.

  1. The words verification engineer and design verification engineer are used interchangeably in the book. They refer to the person performing the design verification tasks.

  2. The words design engineer and designer are used interchangeably in the book. They refer to the person performing the logic design task. Often a logic designer also performs the design verification task.

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