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Chapter 2. Modeling a Verification Environment in e

Before we discuss the details of the e language, it is important to understand the various components of a verification environment built with e. A verification engineer must use "good" techniques to do efficient verification. In this chapter we discuss the high level components of a verification environment and the interaction between them. There are e code examples in this chapter to illustrate the high level components. The syntax details of these examples will be discussed in later chapters. In this chapter, readers should focus only on the high level concepts.

Currently, the Specman Elite tool from Verisity Design[1] supports the e language. We will use this tool as a reference e implementation.[2] We will discuss the interaction between Specman Elite and the Verilog or VHDL simulator.[3] Note that although Specman Elite is used, the concepts explained in this book will apply to any future tools that support the e language.

[1] Please see http://www.verisity.com for details on Specman Elite.

[2] Other tools may support e in the future.

[3] For conciseness, in this book, hereafter we usually will refer to the Verilog or VHDL simulator as simply Simulator or HDL Simulator.

Chapter Objectives

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