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A.10 Simulator Interface Statements and Unit Members

verilog function 'HDL-path'(params) : n; // n is result size in bits

verilog import file-name; // statement only

verilog task 'HDL-path'(params);

verilog time Verilog-timescale; // statement only

vhdl driver 'HDL-path' using option, …; // unit member only

vhdl function 'designator' using option, …;

vhdl procedure 'identifier' using option, …;

vhdl time VHDL-timescale; // statement only

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