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Chapter 1. Overview of Functional Verification

As the average gate count for designs now approaches or exceeds one million, functional verification has become the main bottleneck in the design process. Design teams spend 50% to 70% of their time verifying designs rather than creating new ones. As designs grow more complex, the verification problems increase exponentially—when a design doubles in size, the verification effort can easily quadruple.

Unlike some design tasks, which have been automated with sophisticated logic synthesis or place-and-route tools, functional verification has remained a largely manual process. To eliminate the verification bottleneck, verification engineers have tried incorporating new methodologies and technologies. While various methodologies have evolved, including formal methods, simulation is still the preferred method for verification.

High-level Verification Languages (HVLs) have emerged to solve the functional verification bottleneck. This chapter describes how e, an HVL, can solve the verification bottleneck.

Chapter Objectives

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