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14.1 Traditional Verification Methodology

In a traditional verification methodology, the verification engineer goes through the following steps to verify a DUT (block, chip, or system):

  1. Create a test plan that contains directed tests for the DUT based on the engineer's knowledge of the design specification.

  2. Write the directed tests. The engineer typically spends a lot of manual effort in writing these directed tests. Since the DUT is still evolving at this point, it is impossible to predict where the bugs might be. It is possible that a certain directed test may not uncover any bugs. Moreover, many directed tests may overlap with other directed tests, thus testing the same functionality.

  3. Run the directed tests to find bugs in the DUT. Since the directed tests verify specific scenarios, only bugs pertaining to those specific scenarios are detected. Other scenarios are left uncovered.

  4. Add more directed tests if necessary to cover new scenarios. Engineer spends more manual effort thinking about new scenarios that need to be tested.

  5. Run these additional directed tests to find more bugs in the DUT. Steps 4 and 5 are run until the engineer is convinced that enough directed testing has been done. However, the measurement of adequacy is still very ad hoc.

  6. Random testing is initiated with some form of a random stimulus generator after multiple iterations of steps 4 and 5 are performed.

  7. Random testing uncovers bugs that were not detected originally by directed tests. Random testing often catches corner cases that were missed by the verification engineer. The bugs that are uncovered are therefore fixed in a very late stage of the verification process.

  8. Functional coverage is initiated after multiple iterations of steps 6 and 7 are performed. Functional coverage is run mainly in the post-processing mode and it provides results on the values of interesting items and state transitions. Random simulations are run until desired functional coverage levels are achieved.

  9. After steps 1 through 8 are performed and the coverage results are satisfactory, the verification is considered complete.

Figure 14-1 shows the traditional verification process outlined above.

Figure 14-1. Traditional Verification Methodology

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14.1.1 Problems with a Traditional Verification Methodology

The traditional verification methodology shown in Figure 14-1 has key productivity and quality issues:

Thus, it is clear that many aspects of the traditional verification methodology are inefficient and very manual in nature. The problems with this approach lead to lots of wasted verification time and suboptimal verification quality.

14.1.2 Reasons for using Traditional Verification Methodology

Although there are obvious problems with the traditional verification methodology, verification projects have persisted with this approach over the years. There are some important reasons for this dependence on the traditional verification methodology:

Due to these problems, verification engineers could never take advantage of the coverage-driven functional verification approach that can provide more productivity and higher verification quality. Most of their time was spent on integrating the tools and working with inefficient verification flows, rather than on focusing on DUT verification.

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