This section lists available verification resources on the World Wide Web. Although most of these websites do not directly discuss the e language, it is important for a verification engineer to be familiar with different verification methodologies to choose the technique that is most suitable for a specific verification problem.
Verilog— http://www.verilog.com
Cadence— http://www.cadence.com/
EE Times— http://www.eetimes.com
Synopsys— http://www.synopsys.com/
DVCon (Conference for HDL and HVL Users)— http://www.dvcon.org
Verification Guild— http://www.janick.bergeron.com/guild/default.htm
Deep Chip— http://www.deepchip.com
For details on SystemC, see http://www.systemc.org
Information on Verilog-XL and Verilog-NC is available at http://www.cadence.com
Information on VCS is available at http://www.synopsys.com
Information on hardware acceleration tools is available at the following websites:
Information on in-circuit emulation tools is available at the following websites:
Information on coverage tools is available at the following websites:
Information on assertion checking tools is available at the following websites:
Information on e is available at http://www.verisity.com
Information on Vera is available at http://www.open-vera.com
Information on SystemVerilog is available at http://www.accellera.org
Information on Open Verification Library is available at http://www.accellera.org
Information on equivalence checking tools is available at the following websites:
Information on formal verification tools is available at the following websites: